For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
In the manufacture of integrated circuit devices, multi-gate transistors, such as fin-FET and tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, fin-FET and tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they may enable a less complicated fin-FET and tri-gate fabrication process. In other instances, silicon-on-insulator substrates are preferred because of the improved short-channel behavior of fin-FET and tri-gate transistors.
Scaling multi-gate transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the external resistance (Rext) during performance of such devices have become overwhelming. Many different techniques have been attempted to improve Rext of transistors including improved contact metals, increased activation of dopant and lowered barriers between the semiconductor and contact metal. However, significant improvements are still needed in the area of Rext reduction.